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nxp reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. scm - i.mx 6dual/6quad datasheet for industrial products 1. introduction nxp s ingle c hip s ystem m odules (scm s ) are a suite of highly integrated products in an ultra - small form factor. the first member of this portfol io, the nxp scm - i.mx 6dual/6quad , drastically reduces time to market by providing a solution that minimizes design time. weve integrated and validated dual - and quad - core performance, the power management system, flash memory, and over a hundred passive system components all in the size of a dime. the scm - i.mx 6dual /6quad is enabled with the standard i.mx 6dual/6quad multimedia, connectivity and security features including h igh assurance boot, cryptographic cipher engines, random number generator, and tamper detection . it is a scalable solution intended for use in a wide variety of consumer and industrial applications. the scm - i.mx 6dual/6quad speeds and eases development time by addressing technology challenges such as design of ddr and power management. our single chip module i.mx 6dual/6quad consists of the i.mx 6 dual/6quad applications processor, pf0100 (pmic) for power management, 16 mb spi nor, over a hundred discrete compo nents, and is enabled for lpddr2 via pop assembly . nxp semiconductor, inc. document number: scmimx6dqiec data s heet : technical data rev . 0 , 0 1 /201 7 contents 1. introduction ................................ ................................ ........ 1 1.1. ordering information ................................ ............... 2 1.2. features ................................ ................................ ... 3 1.3. references ................................ ............................... 8 2. architectural overview ................................ ...................... 9 2.1. block diagram ................................ ........................ 9 3. modules list ................................ ................................ ..... 10 3.1. special signal considerations ............................... 10 4. electrical characteristics ................................ .................. 11 4.1. chip - level conditions ................................ .......... 11 5. power supplies requirements and restrictions ................ 12 5.1. power - up sequences ................................ ............. 12 5.2. power - down sequences ................................ ........ 12 5.3. power supplies usage ................................ ........... 12 5.4. power supplies restrictions ................................ .. 12 5.5. boot configuration ................................ ................ 12 6. boot mode configuration ................................ ................. 14 6.1. boot mode configuration pins .............................. 14 6.2. boot devices interfaces allocation ....................... 14 7. package information ................................ ......................... 14 7.1. signal list ................................ ............................. 14 7.2. critical signals ................................ ...................... 21 7.3. ball map ................................ ................................ 24 7.4. package drawings ................................ ................. 26 8. revision history ................................ ............................... 30
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 2 nxp semiconductors 1.1. ordering i nformation figure 1. part number nomenc lature the table below shows examples of orderable part numbers. table 1. part numbers part number cpu part differentiator speed grade temperature grade package mscmmx6dzc k08ab i.mx 6dual 16mb spi nor, pf0100 800 mhz industrial: - 40 to 10 5c scm 14x17mm p0.65mm 2d pop m scmmx6 q zc k08ab i.mx 6quad 16mb spi nor, pf0100 800 mhz industrial: - 4 0 to 10 5c scm 14x17mm p0.65mm 2d pop
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 nxp semiconductors 3 1.2. features 1.2.1. i.mx 6dual/6quad features the i.mx 6dual/6quad processors are based on arm ? cortex ? - a9 mpcore platform, which has the following features: ? arm cortex - a9 mpcore 4xcpu processor (with trustzone?) ? the core configuration is symmetric, where each core includes: 32 kbyte l1 instruction cache 32 kbyte l1 data cache private timer and watchdog cortex - a9 neon mpe (media processing engine) co - processor the arm cortex - a9 mp core complex includes: ? general interrupt controller (gic) with 128 interrupt support ? global timer ? snoop control unit (scu) ? 1 mb unified i/d l2 cache, shared by two/four cores ? two master axi (64 - bit) bus interfaces output of l2 cache ? frequency of the core ( incl uding neon and l1 cache) as per table 5 ? neon mpe coprocessor simd media processing architecture neon register file with 32x64 - bit gener al - purpose registers neon integer execute pipeline (alu, shift, mac) neon dual, single - precision floating point execute pipeline (fadd, fmul) neon load/store and permute pipeline the soc - level memory system consists of the following additional components: boot rom, including hab (96 kb) internal multimedia / shared, fast access ram (ocram, 256 kb) secure/non - secure ram (16 kb) ? external memory interfaces: 32 - bit lpddr2, supporting ddr interleaving mode, or fixed 2x32. 8 - bit nand - flash, including support for raw mlc/slc, 2 kb, 4 kb, and 8 kb page size, ba - nand, pba - nand, lba - nand, onenand? and others. bch ecc up to 40 bit s .
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 4 nxp semiconductors 16/32 - bit nor flash. all eimv2 pins are muxed on other interfaces. 16/32 - bit psram, cellular ram each i.mx 6dual/6quad processor enables t he following interfaces to external devices (some of them are muxed and not available simultaneously): ? hard disk drives sata ii, 3.0 gbps ? displays total of five interfaces available. total raw pixel rate of all interfaces is up to 450 mpixels/sec, 24 bpp. up to four interfaces may be active in parallel. one parallel 24 - bit display port, up to 225 mpixels/sec (for example, wuxga at 60 hz or dual hd1080 and wxga at 60 hz) lvds serial ports one port up to 165 mpixels/sec or two ports up to 85 mp/sec (for examp le, wuxga at 60 hz) each hdmi 1.4 port mipi/dsi, two lanes at 1 gbps ? camera sensors: parallel camera port (up to 20 bit and up to 240 mhz peak) mipi csi - 2 serial camera port, supporting up to 1000 mbps/lane in 1/2/3 - lane mode and up to 800 mbps/lane in 4 - l ane mode. the csi - 2 receiver core can manage one clock lane and up to four data lanes. each i.mx 6dual/6quad processor has four lanes. ? expansion cards: four mmc/sd/sdio card ports all supporting: C 1 - bit or 4 - bit transfer mode specifications for sd and sdio cards up to uhs - i sdr - 104 mode (104 mb/s max) C 1 - bit, 4 - bit, or 8 - bit transfer mode specifications for mmc cards up to 52 mhz in both sdr and ddr modes (104 mb/s max) ? usb: one high speed (hs) usb 2.0 otg (up to 480 mbps), with integrated hs usb phy three usb 2.0 (480 mbps) hosts: C one hs host with integrated high speed phy C two hs hosts with integrated hs - ic usb (high speed inter - chip usb) phy ? expansion pci express port (pcie) v2.0 one lane : pci express (gen 2.0) dual mode complex, supporting root complex op erations and endpoint operations. uses x1 phy configuration. ? miscellaneous ips and interfaces: ssi block capable of supporting audio sample frequencies up to 192 khz stereo inputs and outputs with i2s mode
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 nxp semiconductors 5 esai is capable of supporting audio sample frequen cies up to 260khz in i2s mode with 7.1 multi - channel outputs five uarts, up to 4.0 mbps each: C providing rs232 interface C supporting 9 - bit rs485 multidrop mode C one of the five uarts (uart1) supports 8 - wire while others four supports 4 - wire. this is due to the soc iomux limitation, since all uart ips are identical. five ecspi (enhanced cspi) three i2c, supporting 400 kbps gigabit ethernet controller (ieee1588 compliant), 10/100/1000 1 mbps four pulse width modulators (pwm) system jtag controller (sjc) gpio with interrupt capabilities 8x8 key pad port (kpp) sony philips digital interconnect format (spdif), rx and tx two controller area network (flexcan), 1 mbps each two watchdog timers (wdog) audio mux (audmux) the i.mx 6dual/6quad processors integrate advanced power management unit and controllers: ? provide pmu, including ldo supplies, for on - chip resources ? use temperature sensor for monitoring the die temperature ? support dvfs techniques for low power modes ? use software state retent ion and power gating for arm and mpe ? support various levels of system power modes ? use flexible clock gating control scheme the i.mx 6dual/6quad processors use dedicated hardware accelerators to meet the targeted multimedia performance. the use of hardware accelerators is a key factor in obtainin g high performance at low power consumption numbers, while having the cpu core relatively free for performing other tasks. 1 the theoretical maximum performance of 1 gbps enet is limited to 470 mbps (total for tx and rx) due to internal bus throughput limitations. the actual measured performance in optimized environment is up to 400 mbps. for details, see the err004512 erratum in the i.mx 6dual/6quad errata document imx6dqce .
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 6 nxp semiconductors the i.mx 6dual/6quad processors incorporate the following hardware accelerators: ? vpu video pr ocessing unit ? ipuv3h image processing unit version 3h (2 ipus) ? gpu3dv4 3d graphics processing unit (opengl es 2.0) version 4 ? gpu2dv2 2d graphics processing unit (bitblt) ? gpuvg openvg 1.1 graphics processing unit ? asrc asynchronous sample rate converter secu rity functions are enabled and accelerated by the following hardware: ? arm trustzone including the tz architecture (separation of interrupts, memory mapping, etc.) ? sjc system jtag controller. protecting jtag from debug port attacks by regulating or blocking the access to the system debug features. ? caam cryptographic acceleration and assurance module, containing 16 kb secure ram and true and pseudo random number generator (nist certified) ? snvs secure non - volatile storage, including secure real time clock ? csu central security unit. enhancement for the ic identification module (iim). will be configured during boot and by efuses and will determine the security level operation mode as well as the tz policy. ? a - hab advanced high assurance boot habv4 with the new emb edded enhancements: sha - 256, 2048 - bit rsa key, version control mechanism, warm boot, csu, and tz initialization. 1.2.2. pf0100z features ? input voltage range to pmic: 2.8 - 4.5 v ? buck regulators four to six channel configurable C sw1a/b/c, 4.5 a (single); 0.3 to 1.875 v C sw1a/b, 2.5 a (single/dual); sw1c 2.0 a (independent); 0.3 to 1.875 v C sw2, 2.0 a; 0.4 to 3.3 v C sw3a/b, 2.5 a (single/dual); 0.4 to 3.3 v C sw3a, 1.25 a (independent); sw3b, 1.25 a (independent); 0.4 to 3.3 v C sw4, 1.0 a; 0.4 to 3.3 v C sw4, vtt mode pro vide ddr termination at 50% of sw3a dynamic voltage scaling modes: pwm, pfm, aps
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 nxp semiconductors 7 programmable output voltage programmable current limit programmable soft start programmable pwm switching frequency programmable ocp with fault interrupt ? boost regulator swbst , 5.0 to 5.15 v, 0.6 a, otg support modes: pfm and auto ocp fault interrupt ? ldos six user programmable ldo C vgen1, 0.80 to 1.55 v, 100 ma C vgen2, 0.80 to 1.55 v, 250 ma C vgen3, 1.8 to 3.3 v, 100 ma C vgen4, 1.8 to 3.3 v, 350 ma C vgen5, 1.8 to 3.3 v, 100 ma note vgen5 power characteristics are modified from what is displayed in table 106 of the mmpf0100 datasheet. scm - specific tolerances are 5% , rather than 3% as presented in the table . C vgen6, 1.8 to 3.3 v, 200 ma soft start ldo/switch supply C vsnvs (1.0/1. 1/1.2 /1.3/1.5/1.8/3.0 v) , 400 u a ? ddr memory reference voltage vrefddr, 0.6 to 0.9 v, 10 ma ? 16 mhz internal master clock ? otp(one time programmable) memory for device configuration user programmable start - up sequence and timing ? battery backed memory including coin cell charger ? i2c interface ? user programmable standby, sleep, and off modes
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 8 nxp semiconductors 1.3. references this document is intended to be a companion to the data sheets of the following integrated parts: a) nxp i.mx 6dual/6quad ( document number: imx6dqi ec ) b) nxp mmpf0100 (document number: mmpf0100z ) c) spi nor ( n25q128a13 )
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 nxp semiconductors 9 2. architectural overview the following subsection provides an architectural overview of the scm - i.mx 6dual/6quad . 2.1. block diagram figure 2. scm - i.mx 6dual/6quad block diagram
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: tec hnical data , rev. 0 , 01/2017 10 nxp semiconductors 3. modules list table 2. modules list block name description/notes i.mx 6dual/6quad nxp i.mx 6dual/6quad applications processor. fully functional as a normal i.mx 6dual/6quad except the mlb bus is disabled and not pinned out. mmpf0100 power management ic requires only a single supply and can provide power and voltage references to entire scm. refer to section 4 for electrical details. spi nor 16 megabytes of spi nor which is fully available for user programming. lpddr2 pop interface interfa ce to support lpddr 2 in pop configuration using a 12mm x 12mm fbga216 footprint. discrete components 109 passives for decoupling capacitors and reference resistors. 3.1. special signal considerations the figure below shows critical internal connections, pull - ups and pulldowns. figure 3. scm - i.mx 6dual/6quad critical internal connections note ddr_vref is connected internally to the lpddr2 memory through one of the pop landing pads.
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 nxp semiconductors 11 4. electrical characteristics 4.1. chip - level conditions 4.1.1. absolute max ratings caution stresses b eyond those listed under table 3, 4 and 5 may affect reliability or cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions beyond those indicated in the operating ranges or parameters tables is not implied." table 3. absolute max ratings parameter description symbol min max unit pmic system supply voltage range pmic_vin - 0.3 4.8 v temperature range (storage) t_storage - 40 150 c 4.1.2. thermal resistance table 4 provides the fo - wlp thermal resistance data. table 4. fo - wlp thermal resistance data parameter description test condition symbol value unit junction to ambient 1 ,6 single - layer board (1s); natural convection 2 r ja 36.5 c/w four - layer board (2s2p); natural convection 2 r ja 19.9 c/w junction to ambient 1 ,6 single - layer board (1s); air flow 200ft/min 3 r j m a 27.7 c/w four - layer board (2s2p); air flow 200ft/min 3 r j m a 16.1 c/w junction to board 1,4 ,6 - r jb 6.6 c/w junction to top characterization parameter 1,5 ,6 - jt 2.9 c/w 1 junction temperature is a function of die size, on - chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 per semi g38 - 87 and jedec jesd51 - 2 with the single layer board horizontal. 3 per jedec jesd51 - 6 with the board horizontal. 4 thermal resistance between the die and the printed circuit board per jedec jesd51 - 8. board temperature is measured on the top surface of the board near the package. 5 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51 - 2. when greek letters are not available, the thermal characterization param eter is written as psi - jt. 6 v alues reported are modeled and based upon a summation of power dissipation of multiple die within the package. junction temper atures will vary between die according to power ratios and use case.
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 12 nxp semiconductors 4.1.3. operating range s table 5. operating ran ges parameter description symbol min max unit pmic system supply voltage range pmic_vin 3.6 4.5 v spi nor flash supply voltage range nvcc_eim0_nor 2.7 75 3.6 v junction temperature ( standard industria l ) tj - 40 10 5 c 5. power supplies requirements and restrictions scm - specific power - up sequence requirements are shown in scm - imx6dqhug . 5.1. power - up sequences must follow the i.mx 6dual/6quad industrial datasheet ( document number: imx6dqi ec ) recommendations for power up. the internal pmic simplifies power sequence design. 5.2. power - down sequences must follow the i.mx 6dual/6quad industrial datasheet ( document number: imx6dqi ec ) recommendations fo r power down. 5.3. power supplies usage must follow the i.mx 6dual/6quad industrial datasheet ( document number: imx6dqi ec ) recommendations for power supply usage. 5.4. power supplies restrictions ddr_1v2 and ddr_1v2_sw3afb (switcher 3 feedback pin) are internally connected for dedicated lpddr2 usage with sw3. sw3 cannot be used to supply anything else but the lpddr2. 5.5. boot configuration 5.5.1. otp pmic table 6. otp fuse map registers default configuration pre - programmed otp configuration program code (hex) intended use sw1ab_volt 1.375v 1.375v 2b vddsoc sw1ab_seq 1 2 02 sw1ab config single phase, 2.0 mhz single phase, 2.0 mhz 05
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 nxp semiconductors 13 registers default configuration pre - programmed otp configuration program code (hex) intended use sw1c_volt 1.375 1.375v 00 vddarm sw1c_seq 1 2 02 sw1c config independent, 2.0 mhz independent, 2.0 mhz 00 sw2_volt 3.0v 3.15v 6f vddhigh_in sw2_seq 2 1 01 sw2 config single phase, 2.0 mhz single phase, 2.0 mhz 01 sw3a_volt 1.5v 1.2v 20 ddr 1.2v sw3a_seq 3 4 04 sw3a config single phase, 2.0 mhz single phase, 2.0 mhz 05 sw3b_volt 1.5v 1.2v 20 ddr 1.2v sw3b_seq 3 4 04 sw3b config single phase, 2.0 mhz single phase, 2.0 mhz 01 sw4_volt 1.8v 1.8v 54 ddr 1.8v sw4_seq 3 4 04 sw4_config no vtt, 2.0mhz no vtt, 2.0 mhz 01 swbst_volt - - 00 customer swbst_seq - 4 04 vsnvs_volt 3.0v 3.0v 06 vdd_snvs_in vrefddr_seq 3 4 04 vgen1_volt - - 00 customer vgen1_seq - - 00 vgen2_volt 1.5v - 00 customer vgen2_seq 2 - 00 vgen3_volt - - 00 customer vgen3_seq - - 00 vgen4_volt 1.8v - 00 customer vgen4_seq 3 - 00 vgen5_volt 2.5v - 00 customer vgen5_seq 3 - 00 vgen6_volt 2.8v - 00 customer vgen6_seq 3 - 00 pu config1, seq_clk_speed 1.0ms 1.0ms 01 pu config2, swdvs_clk 6.25 mv/us 12.5mv/us 00 pu config3, pwron level sensitive level sensitive 00 pg en resetbmcu in default mode 00
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 14 nxp semiconductors note 1. refer to application notes an4714 (features of voltage regulators in the mmpf0100) and an4536 (mmpf0100 otp programming instructions) for further usage instructions. 2. the otp registers for regulators which default to (off) are free to be programmed according to customer needs. 3. the otp lock bit is not programmed from factory. 4. nxp not responsible for device issues caused by customer fuse programming. 6. boot mode configurati on 6.1. boot mode configuration pins refer to the i.mx 6dual/6quad industrial datasheet ( document number: imx6dqi ec ). 6.2. boot devices interfaces allocation not limited to booting from internal spi nor. refer to the i.mx 6dual/6quad industrial datasheet ( document number: imx6dqi ec ). 7. package information 7.1. signal list table 7. signal list ball name ball power group comments boot_mode0 u11 vdd_snvs_in boot_mode1 v12 vdd_snvs_in clk1_n u18 vdd_high_cap clk1_p u17 vdd_high_cap clk2_n w19 vdd_high_cap clk2_p w20 vdd_high_cap csi_clk0m n20 nvcc_mipi csi_clk0p n19 nvcc_mipi csi_d0m r20 nvcc_mipi csi_d0p r19 nvcc_mipi csi_d1m p19 nvcc_mipi csi_d1p p20 nvcc_mipi csi_d2m m19 nvcc_mipi csi_d2p m20 nvcc_mipi
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 nxp semiconductors 15 ball name ball power group comments csi_d3m l20 nvcc_mipi csi_d3p l19 nvcc_mipi csi0_dat10 h17 nvcc_csi csi0_dat11 h18 nvcc_csi csi0_dat12 j17 nvcc_csi csi0_dat13 j18 nvcc_csi csi0_dat14 k17 nvcc_csi csi0_dat15 k16 nvcc_csi csi0_dat16 n16 nvcc_csi csi0_dat17 m18 nvcc_csi csi0_dat18 l17 nvcc_csi csi0_dat19 m17 nvcc_csi csi0_dat4 e17 nvcc_csi csi0_dat5 e18 nvcc_csi csi0_dat6 f17 nvcc_csi csi0_dat7 f18 nvcc_csi csi0_dat8 g17 nvcc_csi csi0_dat9 g18 nvcc_csi csi0_data_en d18 nvcc_csi csi0_mclk c18 nvcc_csi csi0_pixclk c17 nvcc_csi csi0_vsync d17 nvcc_csi di0_disp_clk a4 nvcc_lcd di0_pin15 a2 nvcc_lcd di0_pin2 b4 nvcc_lcd di0_pin3 b3 nvcc_lcd di0_pin4 a3 nvcc_lcd disp0_dat0 d5 nvcc_lcd disp0_dat1 c5 nvcc_lcd disp0_dat10 b7 nvcc_lcd disp0_dat11 a7 nvcc_lcd disp0_dat12 d8 nvcc_lcd disp0_dat13 c8 nvcc_lcd disp0_dat14 b8 nvcc_lcd disp0_dat15 a8 nvcc_lcd disp0_dat16 d9 nvcc_lcd disp0_dat17 c9 nvcc_lcd disp0_dat18 b9 nvcc_lcd disp0_dat19 a9 nvcc_lcd disp0_dat2 b5 nvcc_lcd
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical dat a , rev. 0 , 01/2017 16 nxp semiconductors ball name ball power group comments disp0_dat20 d10 nvcc_lcd disp0_dat21 c10 nvcc_lcd disp0_dat22 b10 nvcc_lcd disp0_dat23 a10 nvcc_lcd disp0_dat3 a5 nvcc_lcd disp0_dat4 d6 nvcc_lcd disp0_dat5 c6 nvcc_lcd disp0_dat6 b6 nvcc_lcd disp0_dat7 a6 nvcc_lcd disp0_dat8 d7 nvcc_lcd disp0_dat9 c7 nvcc_lcd dsi_clk0m p18 nvcc_mipi dsi_clk0p p17 nvcc_mipi dsi_d0m r17 nvcc_mipi dsi_d0p r18 nvcc_mipi dsi_d1m n17 nvcc_mipi dsi_d1p n18 nvcc_mipi eim_a16 h1 nvcc_eim1 eim_a17 h4 nvcc_eim1 eim_a18 j2 nvcc_eim1 eim_a19 j3 nvcc_eim1 eim_a20 j4 nvcc_eim1 eim_a21 k1 nvcc_eim1 eim_a22 k2 nvcc_eim1 eim_a23 k3 nvcc_eim1 eim_a24 k4 nvcc_eim1 eim_a25 r5 nvcc_eim0 eim_bclk b1 nvcc_eim2 eim_cs0 h3 nvcc_eim1 eim_cs1 h2 nvcc_eim1 eim_d16_nor v3 nvcc_eim0 _nor eim_d17_nor u4 nvcc_eim0 _nor eim_d18_nor u3 nvcc_eim0 _nor eim_d19 t4 nvcc_eim0 _nor eim_d20 t3 nvcc_eim0 _nor eim_d21 r4 nvcc_eim0 _nor eim_d22 p3 nvcc_eim0 _nor eim_d23 p4 nvcc_eim0 _nor eim_d24 t5 nvcc_eim0 _nor eim_d25 n3 nvcc_eim0 _nor
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 nxp semiconductors 17 ball name ball power group comments eim_d26 m4 nvcc_eim0 _nor eim_d27 m3 nvcc_eim0 _nor eim_d28 l4 nvcc_eim0 _nor eim_d29 l3 nvcc_eim0 _nor eim_d30 l2 nvcc_eim0 _nor eim_d31 l1 nvcc_eim0 _nor eim_da0 e1 nvcc_eim2 eim_da1 f4 nvcc_eim2 eim_da10 d2 nvcc_eim2 eim_da11 d4 nvcc_eim2 eim_da12 c4 nvcc_eim2 eim_da13 b2 nvcc_eim2 eim_da14 c2 nvcc_eim2 eim_da15 c3 nvcc_eim2 eim_da2 f2 nvcc_eim2 eim_da3 f3 nvcc_eim2 eim_da4 e2 nvcc_eim2 eim_da5 d1 nvcc_eim2 eim_da6 e4 nvcc_eim2 eim_da7 e3 nvcc_eim2 eim_da8 c1 nvcc_eim2 eim_da9 d3 nvcc_eim2 eim_eb0 g3 nvcc_eim2 eim_eb1 g2 nvcc_eim2 eim_eb2_nor v4 nvcc_eim0 _nor eim_eb3 n4 nvcc_eim0 _nor eim_lba f1 nvcc_eim1 eim_oe g1 nvcc_eim1 eim_rw g4 nvcc_eim1 eim_wait f5 nvcc_eim2 enet_crs_dv d11 nvcc_enet enet_mdc d12 nvcc_enet enet_mdio c12 nvcc_enet enet_ref_clk c13 nvcc_enet enet_rx_er c11 nvcc_enet enet_rxd0 a11 nvcc_enet enet_rxd1 b11 nvcc_enet enet_tx_en d13 nvcc_enet enet_txd0 a12 nvcc_enet enet_txd1 b12 nvcc_enet
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 18 nxp semiconductors ball name ball power group comments gpio_0 e16 nvcc_gpio gpio_1 e15 nvcc_gpio gpio_16 m15 nvcc_gpio gpio_17 r16 nvcc_gpio gpio_18_pmic_intb ad12 nvcc_gpio gpio_19 p16 nvcc_gpio gpio_2 d16 nvcc_gpio gpio_3 a19 nvcc_gpio gpio_4 f16 nvcc_gpio gpio_5 g16 nvcc_gpio gpio_6 h16 nvcc_gpio gpio_7 j16 nvcc_gpio gpio_8 l16 nvcc_gpio gpio_9 m16 nvcc_gpio hdmi_clkm k19 hdmi_vph hdmi_clkp k20 hdmi_vph hdmi_d0m j19 hdmi_vph hdmi_d0p j20 hdmi_vph hdmi_d1m g19 hdmi_vph hdmi_d1p g20 hdmi_vph hdmi_d2m f19 hdmi_vph hdmi_d2p f20 hdmi_vph hdmi_hpd k18 hdmi_vph jtag_mod u19 nvcc_jtag jtag_tck t17 nvcc_jtag jtag_tdi v18 nvcc_jtag jtag_tdo v17 nvcc_jtag jtag_tms t18 nvcc_jtag jtag_trst_b t16 nvcc_jtag key_col0 e12 nvcc_gpio key_col1 e13 nvcc_gpio key_col2 c14 nvcc_gpio key_col3_pmic_scl w13 nvcc_gpio key_col4 c15 nvcc_gpio key_row0 e11 nvcc_gpio key_row1 f14 nvcc_gpio key_row2 d14 nvcc_gpio key_row3_pmic_sda w12 nvcc_gpio key_row4 d15 nvcc_gpio lvds0_clk_n b19 nvcc_lvds_2p5
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 nxp semiconductors 19 ball name ball power group comments lvds0_clk_p b20 nvcc_lvds_2p5 lvds0_tx0_n e19 nvcc_lvds_2p5 lvds0_tx0_p e20 nvcc_lvds_2p5 lvds0_tx1_n d19 nvcc_lvds_2p5 lvds0_tx1_p d20 nvcc_lvds_2p5 lvds0_tx2_n c19 nvcc_lvds_2p5 lvds0_tx2_p c20 nvcc_lvds_2p5 lvds0_tx3_n a18 nvcc_lvds_2p5 lvds0_tx3_p b18 nvcc_lvds_2p5 lvds1_clk_n a16 nvcc_lvds_2p5 lvds1_clk_p b16 nvcc_lvds_2p5 lvds1_tx0_n a17 nvcc_lvds_2p5 lvds1_tx0_p b17 nvcc_lvds_2p5 lvds1_tx1_n b15 nvcc_lvds_2p5 lvds1_tx1_p a15 nvcc_lvds_2p5 lvds1_tx2_n b14 nvcc_lvds_2p5 lvds1_tx2_p a14 nvcc_lvds_2p5 lvds1_tx3_n a13 nvcc_lvds_2p5 lvds1_tx3_p b13 nvcc_lvds_2p5 nandf_ale u15 nvcc_nandf nandf_cle t15 nvcc_nandf nandf_cs0 t14 nvcc_nandf nandf_cs1 y16 nvcc_nandf nandf_cs2 w16 nvcc_nandf nandf_cs3 u16 nvcc_nandf nandf_d0 r13 nvcc_nandf nandf_d1 t13 nvcc_nandf nandf_d2 r12 nvcc_nandf nandf_d3 t12 nvcc_nandf nandf_d4 r11 nvcc_nandf nandf_d5 t11 nvcc_nandf nandf_d6 r10 nvcc_nandf nandf_d7 t10 nvcc_nandf nandf_rb0 u14 nvcc_nandf nandf_wp_b v16 nvcc_nandf nor_hold_b v13 nvcc_eim0 nor_w_b aa13 nvcc_eim0 onoff ad13 vdd_snvs_in pcie_rxm y20 pcie_vph pcie_rxp y19 pcie_vph
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 20 nxp semiconductors ball name ball power group comments pcie_txm aa19 pcie_vph pcie_txp aa20 pcie_vph rgmii_rd0 n1 nvcc_rgmii rgmii_rd1 n2 nvcc_rgmii rgmii_rd2 m1 nvcc_rgmii rgmii_rd3 m2 nvcc_rgmii rgmii_rx_ctl p2 nvcc_rgmii rgmii_rxc p1 nvcc_rgmii rgmii_td0 t1 nvcc_rgmii rgmii_td1 t2 nvcc_rgmii rgmii_td2 r1 nvcc_rgmii rgmii_td3 r2 nvcc_rgmii rgmii_tx_ctl u2 nvcc_rgmii rgmii_txc u1 nvcc_rgmii rtc_xtali v19 vdd_snvs_cap rtc_xtalo v20 vdd_snvs_cap sata_rxm ae17 sata_vph sata_rxp ad17 sata_vph sata_txm ae18 sata_vph sata_txp ad18 sata_vph sd1_clk ae14 nvcc_sd1 sd1_cmd ad14 nvcc_sd1 sd1_dat0 ae16 nvcc_sd1 sd1_dat1 ad16 nvcc_sd1 sd1_dat2 ae15 nvcc_sd1 sd1_dat3 ad15 nvcc_sd1 sd2_clk ab13 nvcc_sd2 sd2_cmd ac13 nvcc_sd2 sd2_dat0 ab14 nvcc_sd2 sd2_dat1 ab12 nvcc_sd2 sd2_dat2 ac12 nvcc_sd2 sd2_dat3 ac14 nvcc_sd2 sd3_clk ac17 nvcc_sd3 sd3_cmd ac16 nvcc_sd3 sd3_dat0 ac18 nvcc_sd3 sd3_dat1 ab17 nvcc_sd3 sd3_dat2 ab18 nvcc_sd3 sd3_dat3 aa17 nvcc_sd3 sd3_dat4 y17 nvcc_sd3 sd3_dat5 y18 nvcc_sd3
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 nxp semiconductors 21 ball name ball power group comments sd3_dat6 w17 nvcc_sd3 sd3_dat7 w18 nvcc_sd3 sd3_rst ab16 nvcc_sd3 sd4_clk p9 nvcc_nandf sd4_cmd n9 nvcc_nandf sd4_dat0 n8 nvcc_nandf sd4_dat1 p8 nvcc_nandf sd4_dat2 n7 nvcc_nandf sd4_dat3 p7 nvcc_nandf sd4_dat4 n6 nvcc_nandf sd4_dat5 p6 nvcc_nandf sd4_dat6 n5 nvcc_nandf sd4_dat7 p5 nvcc_nandf sys_por_b ae12 vdd_snvs_in sys_pwron ae13 vdd_snvs_in sys_stby_req ab15 vdd_snvs_in tamper u13 vdd_snvs_in test_mode r9 vdd_snvs_in usb_h1_dn ad20 vdd_usb_cap usb_h1_dp ad19 vdd_usb_cap usb_otg_chd_b ab19 vdd_usb_cap usb_otg_dn ac19 vdd_usb_cap usb_otg_dp ac20 vdd_usb_cap xtali t19 nvcc_pll xtalo t20 nvcc_pll 7.2. critical signals the table below shows the differences between the ball map of the i.mx6 dual and the scm - i.mx 6dual/6quad . table 8. signal name differences from i.mx6 dual scm - i.mx 6dual/6quad i.mx6 dual remarks ball name ball ball name eim_d16_nor v3 eim_d16 connected to spi nor through a 33ohm resistor eim_d17_nor u4 eim_d17 connected to spi nor eim_d18_nor u3 eim_d18 connected to spi nor eim_eb2_nor v4 eim_eb2 connected to spi nor gpio_18_pmic_intb ad12 gpio_18 i.mx 6dual/6quad q (gpio18) connected to pmic (intb) key_col3_pmic_scl w13 key_col3 i.mx6dq (key_col3) tied to pmic (scl) key_row3_pmic_sda w12 key_row3 i.mx6dq (key_row3) tied to pmic (sda)
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/ 2017 22 nxp semiconductors scm - i.mx 6dual/6quad i.mx6 dual remarks ball name ball ball name nor_hold_b v13 spi nor hold_b nor_w_b aa13 spi nor w_b pmic_ictest y8 pmic ictest pmic_sdwnb y13 pmic sdwnb sys_por_b ae12 por_b i.mx6dq (por_b) connected to pmic (resetbmcu) sys_pwron ae13 pmic_on_req i.mx6dq (pmic_on_req) connected to pmic (pwron) sys_stby_req ab15 pmic_stby_req i.mx6dq (pmic_stby_req) connected to pmic (standby) C C csi_rext grounded internally C C dsi_rext grounded internally C C fa_ana grounded internally C C hdmi_ref grounded internally C C mlb_cn not pinned out. C C mlb_cp not pinned out. C C mlb_dn not pinned out. C C mlb_dp not pinned out. C C mlb_sn not pinned out. C C mlb_sp not pinned out. C C pcie_rext grounded internally C C sata_rext grounded internally C C zqpad tied to ground through 240ohm resistor. the table below shows the device list for ground, power, sense, and reference contact signals table 9. supply signal list for i.mx6 dual supply name balls remark ddr_1v2 e5, e9, e14, v15 ddr_1v2_sw3 a fb w8 ddr_1v8 v5 gpanaio u12 test signal. should be unconnected. gnd a1, c16, u9, v6, w4, w9, y4, y5, e10, e6, e7, e8, f10, f11, f6, f7, f8, a20, f9, g10, g11, g12, g14, g6, g7, g9, h10, h11, aa12, h12, h14, h20, h9, j1, j10, j11, j12, j13, j14, aa14, j7, j8, j9, k10, k11, k12, k7, k8, k9, l10, aa15, l11, l12, l18, l7, l8, l9, r3, r6, r7, r8, aa16, u20, v10, v11, v14, v2, w11, w14, w15, y12, y14, aa18, y15, aa3, aa4, aa5, aa6, aa7, aa8, aa9, ab11, ab3, ac15, ab4, ab5, ab6, ab7, ab8, ab9, ac4, ac5, ac6, ac7,
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 nxp semiconductors 23 supply name balls remark ae20, ac8, ac9, ae1, t6, t7, t8, t9, u6, u7, u8 hdmi_ddccec h19 hdmi_vp l14 hdmi_vph k14 licell y11 licell output from pmic nvcc_csi h15 nvcc_eim0_nor l5 eim0 domain shared with the spi nor. nvcc_eim1 k5 nvcc_eim2 j5 nvcc_enet g5 nvcc_gpio g15 nvcc_jtag p15 nvcc_lcd h5 nvcc_lvds2p5 f15 nvcc_mipi m14 nvcc_nandf p10 nvcc_pll_out r14 nvcc_rgmii m5 nvcc_sd1 m6 nvcc_sd2 n10 nvcc_sd3 p11 pcie_vp n15 pcie_vph n12 pcie_vptx n14 pmic_vcoreref ad9 pmic v_core_ref pmic_vddotp y9 pmic vdd otp pmic_vin ac10, ae11, ae2, ae3, v7, v8, ac11, ac2, ac3, ad10, ad11, ad2, ad3, ae10 main system supply. sata_vp n13 sata_vph n11 sw1abfb ae9 sw1ablx ad7, ad8, ae6, ae7, ae8 sw1cfb ae5 sw1clx ad4, ad5, ad6, ae4 sw2lx w1, w2, w3, y1, y2, y3 sw3ablx w6, w7, y6, y7 sw4lx aa1, aa2, ab2 swbstfb y10 swbstin ab10 swbstlx aa10, aa11
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 24 nxp semiconductors supply name balls remark sys_sw2fb_vin2 v1 sys_sw4fb_vin1 ab1 sys_vsnvs w10 i.mx 6d/6q (vdd_snvs_in) tied to pmic (vsnvs) usb_h1_vbus ae19 usb_otg_vbus ab20 vdd_snvs_cap p12 vddarm_cap m10, m11, m12 vddarm_in m7, m8, m9 vddarm23_cap k13, l13, m13 vddarm23_in j15, k15, l15 vddhigh_cap p14 vddhigh_in r15 vddpu_cap j6, k6, l6 vddsoc_cap f12, f13, g13, h13 vddsoc_in g8, h6, h7, h8 vddusb_cap p13 vgen1 ad1 vgen2 ac1 vgen3 u5 vgen4 w5 vgen5 v9 vgen6 u10 7.3. ball map table 10. ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a gnd di0_pin15 di0_pin4 di0_disp_cl k disp0_dat3 disp0_dat7 disp0_dat11 disp0_dat15 disp0_dat19 disp0_dat23 enet_rxd0 enet_txd0 lvds1_tx3_ n lvds1_tx2_p lvds1_tx1_p lvds1_clk_ n lvds1_tx0_ n lvds0_tx3_ n gpio_3 gnd b eim_bclk eim_da13 di0_pin3 di0_pin2 disp0_dat2 disp0_dat6 disp0_dat10 disp0_dat14 disp0_dat18 disp0_dat22 enet_rxd1 enet_txd1 lvds1_tx3_p lvds1_tx2_ n lvds1_tx1_ n lvds1_clk_p lvds1_tx0_p lvds0_tx3_p lvds0_clk_ n lvds0_clk_p c eim_da8 eim_da14 eim_da15 eim_da12 disp0_dat1 disp0_dat5 disp0_dat9 disp0_dat13 disp0_dat17 disp0_dat21 enet_rx_er enet_mdio enet_ref_cl k key_col2 key_col4 gnd csi0_pixclk csi0_mclk lvds0_tx2_ n lvds0_tx2_p d eim_da5 eim_da10 eim_da9 eim_da11 disp0_dat0 disp0_dat4 disp0_dat8 disp0_dat12 disp0_dat16 disp0_dat20 enet_crs_d v enet_mdc enet_tx_en key_row2 key_row4 gpio_2 csi0_vsync csi0_data_e n lvds0_tx1_ n lvds0_tx1_p
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 nxp semiconductors 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 e eim_da0 eim_da4 eim_da7 eim_da6 ddr_1v2 gnd gnd gnd ddr_1v2 gnd key_row0 key_col0 key_col1 ddr_1v2 gpio_1 gpio_0 csi0_dat4 csi0_dat5 lvds0_tx0_ n lvds0_tx0_p f eim_lba eim_da2 eim_da3 eim_da1 eim_wait gnd gnd gnd gnd gnd gnd vddsoc_cap vddsoc_cap key_row1 nvcc_lvds2 p5 gpio_4 csi0_dat6 csi0_dat7 hdmi_d2m hdmi_d2p g eim_oe eim_eb1 eim_eb0 eim_rw nvcc_enet gnd gnd vddsoc_in gnd gnd gnd gnd vddsoc_cap gnd nvcc_gpio gpio_5 csi0_dat8 csi0_dat9 hdmi_d1m hdmi_d1p h eim_a16 eim_cs1 eim_cs0 eim_a17 nvcc_lcd vddsoc_in vddsoc_in vddsoc_in gnd gnd gnd gnd vddsoc_cap gnd nvcc_csi gpio_6 csi0_dat10 csi0_dat11 hdmi_ddcc ec gnd j gnd eim_a18 eim_a19 eim_a20 nvcc_eim2 vddpu_cap gnd gnd gnd gnd gnd gnd gnd gnd vddarm23_i n gpio_7 csi0_dat12 csi0_dat13 hdmi_d0m hdmi_d0p k eim_a21 eim_a22 eim_a23 eim_a24 nvcc_eim1 vddpu_cap gnd gnd gnd gnd gnd gnd vddarm23_ cap hdmi_vph vddarm23_i n csi0_dat15 csi0_dat14 hdmi_hpd hdmi_clkm hdmi_clkp l eim_d31 eim_d30 eim_d29 eim_d28 nvcc_eim0_ nor vddpu_cap gnd gnd gnd gnd gnd gnd vddarm23_ cap hdmi_vp vddarm23_i n gpio_8 csi0_dat18 gnd csi_d3p csi_d3m m rgmii_rd2 rgmii_rd3 eim_d27 eim_d26 nvcc_rgmii nvcc_sd1 vddarm_in vddarm_in vddarm_in vddarm_ca p vddarm_ca p vddarm_ca p vddarm23_ cap nvcc_mipi gpio_16 gpio_9 csi0_dat19 csi0_dat17 csi_d2m csi_d2p n rgmii_rd0 rgmii_rd1 eim_d25 eim_eb3 sd4_dat6 sd4_dat4 sd4_dat2 sd4_dat0 sd4_cmd nvcc_sd2 sata_vph pcie_vph sata_vp pcie_vptx pcie_vp csi0_dat16 dsi_d1m dsi_d1p csi_clk0p csi_clk0m p rgmii_rxc rgmii_rx_ct l eim_d22 eim_d23 sd4_dat7 sd4_dat5 sd4_dat3 sd4_dat1 sd4_clk nvcc_nand f nvcc_sd3 vdd_snvs_c ap vddusb_cap vddhigh_ca p nvcc_jtag gpio_19 dsi_clk0p dsi_clk0m csi_d1m csi_d1p r rgmii_td2 rgmii_td3 gnd eim_d21 eim_a25 gnd gnd gnd test_mode nandf_d6 nandf_d4 nandf_d2 nandf_d0 nvcc_pll_o ut vddhigh_in gpio_17 dsi_d0m dsi_d0p csi_d0p csi_d0m t rgmii_td0 rgmii_td1 eim_d20 eim_d19 eim_d24 gnd gnd gnd gnd nandf_d7 nandf_d5 nandf_d3 nandf_d1 nandf_cs0 nandf_cle jtag_trst_b jtag_tck jtag_tms xtali xtalo u rgmii_txc rgmii_tx_ct l eim_d18_no r eim_d17_no r vgen3 gnd gnd gnd gnd vgen6 boot_mode 0 gpanaio tamper nandf_rb0 nandf_ale nandf_cs3 clk1_p clk1_n jtag_mod gnd
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 26 nxp semiconductors 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 v sys_sw2fb_ vin2 gnd eim_d16_no r eim_eb2_no r ddr_1v8 gnd pmic_vin pmic_vin vgen5 gnd gnd boot_mode 1 nor_hold_ b gnd ddr_1v2 nandf_wp_ b jtag_tdo jtag_tdi rtc_xtali rtc_xtalo w sw2lx sw2lx sw2lx gnd vgen4 sw3ablx sw3ablx ddr_1v2_s w3afb gnd sys_vsnvs gnd key_row3_p mic_sda key_col3_p mic_scl gnd gnd nandf_cs2 sd3_dat6 sd3_dat7 clk2_n clk2_p y sw2lx sw2lx sw2lx gnd gnd sw3ablx sw3ablx pmic_ictest pmic_vddot p swbstfb licell gnd pmic_sdwn b gnd gnd nandf_cs1 sd3_dat4 sd3_dat5 pcie_rxp pcie_rxm aa sw4lx sw4lx gnd gnd gnd gnd gnd gnd gnd swbstlx swbstlx gnd nor_w_b gnd gnd gnd sd3_dat3 gnd pcie_txm pcie_txp ab sys_sw4fb_ vin1 sw4lx gnd gnd gnd gnd gnd gnd gnd swbstin gnd sd2_dat1 sd2_clk sd2_dat0 sys_stby_re q sd3_rst sd3_dat1 sd3_dat2 usb_otg_ch d_b usb_otg_vb us ac vgen2 pmic_vin pmic_vin gnd gnd gnd gnd gnd gnd pmic_vin pmic_vin sd2_dat2 sd2_cmd sd2_dat3 gnd sd3_cmd sd3_clk sd3_dat0 usb_otg_d n usb_otg_dp ad vgen1 pmic_vin pmic_vin sw1clx sw1clx sw1clx sw1ablx sw1ablx pmic_vcore ref pmic_vin pmic_vin gpio_18_pm ic_intb onoff sd1_cmd sd1_dat3 sd1_dat1 sata_rxp sata_txp usb_h1_dp usb_h1_dn ae gnd pmic_vin pmic_vin sw1clx sw1cfb sw1ablx sw1ablx sw1ablx sw1abfb pmic_vin pmic_vin sys_por_b sys_pwron sd1_clk sd1_dat2 sd1_dat0 sata_rxm sata_txm usb_h1_vbu s gnd 7.4. package drawing s figure 4. scm - i.mx 6dual/6quad without memory
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 nxp semiconductors 27
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 28 nxp semiconductors
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 nxp semiconductors 29
scm - i.mx 6dual /6quad datasheet for industrial products , data sheet: technical data , rev. 0 , 01/2017 30 nxp semiconductors 8. revision history revision date change description 0 01/2017 technical data sheet

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